The present invention relates to the fabrication of semiconductor devices, and more particularly, to the fabrication of contacts for a semiconductor device.
As the integration density of semiconductor devices has increased and the semiconductor devices have been changed into three-dimensional structures, the use of contact holes having high aspect ratios also has increased. However, when a contact hole having a high aspect ratio is filled with a conductive material, such as a doped polysilicon, contact resistance may increase over that of a lower aspect ratio contact hole. The increased contact resistance may cause power dissipation to increase which may impede high-speed operations.
Fabricating a semiconductor device with a contact hole filled with doped polysilicon may include forming a gate pattern on a p-type semiconductor substrate. Next, an n-type impurity region, which may be a source/drain region, is formed in the semiconductor substrate on both sides of the gate pattern. An interlayer dielectric (ILD) is then formed on the surface of the semiconductor substrate, and a contact hole is formed so as to expose a portion of the n-type impurity region. Afterwards, a contact plug is deposited using a doped polysilicon to fill the contact hole. Thus, the source/drain region, which may be an n-type impurity region formed in the semiconductor substrate, may be electrically connected to an upper layer formed on the contact plug.
A method of improving contact resistance by treating (e.g., cleaning) the surface of the source/drain region, so as to decrease a contact resistance between the source/drain region and the contact plug is disclosed in the U.S. Pat. No. 5,534,460 entitled “Optimized contact plug process,” dated Jul. 9, 1996. In this method, a native oxide layer is removed from the inside of a contact hole, and then the contact hole is filled with a doped polysilicon as a contact plug.